I am new to FPGAs. I have a Terasic DE0 Nano. Would I be able to get the J1 running on it with the Verilog code, or do I need to translate it? Does the DE0 Nano have what it takes? I appreciate if you could answer my beginner questions. Thanks.

You'll need to change the RAM primitive to the Altera equivalent, but it should fit just fine. Then you have to figure out how you're going to interface to it.

I'll sign up for that, but I'm actually more interested in a Processing-like environment for Forth. Do you have any suggestions?