You are entirely correct, but I would like to point out that there are Cyclone V cores running logic ~140MHz, not just RAM clocks, and the power consumption is nowhere near that.
Getting a large design that passes timing at that frequency with the Cyclone V fabric is unlikely, however.
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The distinction here, being that more capable FPGAs can get up to the 600MHz+ range, and actually run a full design at that speed.
Getting a large design that passes timing at that frequency with the Cyclone V fabric is unlikely, however.
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The distinction here, being that more capable FPGAs can get up to the 600MHz+ range, and actually run a full design at that speed.