Doesn't Rosetta infringe on Intel's copyrighted instruction set and architecture of a CPU? Why Apple can use this instruction set and others cannot?
UPD: and ARM seems to be infringing as well:
> There’s a standard ARM alternate floating-point behaviour extension (FEAT_AFP) from ARMv8.7, but the M1 design predates the v8.7 standard, so Rosetta 2 uses a non-standard implementation.
> (What a coincidence – the “alternative” happens to exactly match x86.
Good luck persuading a judge that this was "a coincidence".
You can copyright code / implementation but you can't copyright the behaviour of an individual instruction!
It's very unlikely but there could conceivably be a patent, but it would have long since expired.
No case to answer.
Edit: Just to clarify - referring to treatment of one instruction here. As peer comment has said Rosetta translates ISA rather than implements so it's even further removed from being a copyright issue.
> It's very unlikely but there could conceivably be a patent, but it would have long since expired.
For those who weren't following the 32-bit to 64-bit transition on the x86 world back then, the x86-64 ISA is from the year 2000 (https://web.archive.org/web/20000817014037/http://www.x86-64...), so any patent which applies to that ISA (without the ISA being prior art for the patent) is now over 20 years old.
> x86-64/AMD64 was solely developed by AMD. AMD holds patents on techniques used in AMD64; those patents must be licensed from AMD in order to implement AMD64
Thanks. I guess I was thinking that any patents on the instruction in the original article and of FP behaviour would predate 64-bit, but you're right that there could be relevant patents on x86-64.
Thinking aloud, I wonder if AVX 512 is translated?
The edit OP made now includes that Apple Silicon may infringe, but original wording was just Rosetta. Rosetta isn't infringing, because it's not actually implementing anything other than translation. It is possible AS is infringing on a patent, but that wasn't there originally in the post. New context changes the discussion.
UPD: and ARM seems to be infringing as well:
> There’s a standard ARM alternate floating-point behaviour extension (FEAT_AFP) from ARMv8.7, but the M1 design predates the v8.7 standard, so Rosetta 2 uses a non-standard implementation.
> (What a coincidence – the “alternative” happens to exactly match x86.
Good luck persuading a judge that this was "a coincidence".