No, he detailed specific differences in the branch predictors of the two mentioned architectures. Branch prediction is part of the microarchitecture of a CPU, not its ISA. These two should not be confused.
As the other commenter pointed out, I'm talking about instruction predication (also called conditional execution) instead of branch prediction. In any ISA you have branches that might or might not execute depending on some conditions. With ARM, the first four bits of every single instruction - not just branches but loads and stores, addition and subtraction, etc - are used to specify under what conditions the instruction will be executed - so you can have small 'if' statements that don't actually need any branches when they're compiled.
All that is really pretty awesome if you're designing your processor to go in order, but if you want to try out of order execution it becomes more complicated. Now you have to check every instruction to see if its predicated, and if it is you now have a new dependency on the previous arithmetic instruction even if there isn't any data dependency between the two. Of course you could argue that if you find a predicated instruction in ARM code then its replacing a branch that would be in x86 code, and that overall your job is no harder. And you could go back and forth arguing over it.
The important thing to remember, though, is the things that give the ARM ISA inherent advantages when you're making low power, in order processors aren't necessarily advantages when you're talking about high performance, high power processors.
If the inefficiency of the x86 ISA was a killer, we'd all be using Alpha, PowerPC, SPARC, PA-RISC, or Itanium processors today. The basic argument you're giving is about 20 years old by now and the market has seen it tested.
