Take a good look at this deep dive on the Samsung M3 core. Its an ARMv8 processor, which is a fairly orthodox RISC in its capabilities. A RISC-V processor of similar capabilities would have a similar structure. The ISA simply doesn't help all that much at the very high-end.
The advantage of working with RISC-V over ARM right now is that you can configure a RV core to have far less capability than an ARM core. You can license RTL from SiFive for RV64imc (64-bit address and data, baseline integer instruction set, hardware multiply, and 16-bit compressed instructions). Such a core simply does not exist in the ARM marketplace today, partially because NEON is mandatory in ARMv8.
https://www.anandtech.com/show/13199/hot-chips-2018-samsungs...
The advantage of working with RISC-V over ARM right now is that you can configure a RV core to have far less capability than an ARM core. You can license RTL from SiFive for RV64imc (64-bit address and data, baseline integer instruction set, hardware multiply, and 16-bit compressed instructions). Such a core simply does not exist in the ARM marketplace today, partially because NEON is mandatory in ARMv8.