There is a successor called Noel-V: https://www.gaisler.com/index.php/products/processors/noel-v

There is the PULP project (http://www.pulp-platform.org/) by ETH Zurich and University of Bologna with different open-source RISCV cores written in (System) Verilog.

Not exactly true. There exist different tapeouts in academia (e.g. http://asic.ethz.ch/2016/Patronus.html or http://asic.ethz.ch/2015/Imperio.html) as well as in industry (which are not public).

CI is still free. For public repos nothing changes related to CI. For private repos, the build time is limited. However, you always can use a custom runner for your private repo to have unlimited minutes.

You can always start playing around with PULPino on a FPGA :)

You can start playing on FPGAs. There are prebuilt Xilinx images for PULPino :)

You may want to try PULPino: http://www.pulp-platform.org/

The lowRISC team (http://www.lowrisc.org/) aims to develop a Linux capable open source SoC based on RISC-V. They want to use the PULPino RI5CY for their minion cores.

The PULP team added a release plan how they proceed with open source: http://www.pulp-platform.org/release-plan/

* f32c https://github.com/f32c/f32c