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Opensouce RISC-V CPU core implemented in Verilog from scratch in one night
(
github.com/darklife
)
4 points
by
delduca
11 months ago
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past
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4 comments
Open source RISC-V implemented from scratch in one night
(
github.com/darklife
)
272 points
by
guigg
on Aug 27, 2018
|
past
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109 comments
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